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THC63LVD103 _Rev2.2
THC63LVD103
135MHz 30Bits COLOR LVDS Transmitter
General Description
The THC63LVD103 transmitter is designed to support pixel data transmission between Host and Flat Panel Display from NTSC up to SXGA+ resolutions. The THC63LVD103 converts 35bits of CMOS/TTL data into LVDS(Low Voltage Differential Signaling) data stream. The transmitter can be programmed for rising edge or falling edge clocks through a dedicated pin. At a transmit clock frequency of 135MHz, 30bits of RGB data and 5bits of timing and control data (HSYNC, VSYNC, DE, CNTL1, CNTL2) are transmitted at an effective rate of 945Mbps per LVDS channel.
Features
* Wide dot clock range: 8-135MHz suited for NTSC,
VGA, SVGA, XGA,SXGA and SXGA+
* * * * * * * * *
PLL requires no external components Supports spread spectrum clock generator On chip jitter filtering Clock edge selectable Supports reduced swing LVDS for low EMI Power down mode Low power single 3.3V CMOS design 64pin TQFP Backward compatible with THC63LVDM63R(18bits) / M83R(24bits)
Block Diagram
CMOS/TTL INPUT
TA0-6 7
LVDS OUTPUT
TA +/-
TB0-6
7 7
PARALLEL TO SERIAL
TB +/-
TC0-6
TD0-6 TE0-6
TC +/-
7
TD +/-
7
TE +/-
CLK IN (8 to135MHz) RS R/F /PDWN
PLL
TCLK +/(8 to 135MHz)
Copyright 2001-2006 THine Electronics, Inc. All rights reserved.
1
THine Electronics, Inc.
THC63LVD103 _Rev2.2
Pin Out
TB6 TC0 VCC TC1 TC2 TC3 TC4 GND TC5 TC6 TD0 R/F TD1 TD2 TD3 TD4
49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
TB5 GND TB4 TB3 TB2 RS TB1 TB0 TA6 GND TA5 TA4 TA3 TA2 TA1 TA0
LVDS GND TATA+ TBTB+ LVDS VCC LVDS GND TCTC+ TCLKTCLK+ TDTD+ TETE+ LVDS GND
Copyright 2001-2006 THine Electronics, Inc. All rights reserved.
TD5 GND TD6 TE0 TE1 TE2 VCC TE3 TE4 GND TE5 CLK IN /PDWN PLL GND PLL VCC TE6
2
THine Electronics, Inc.
THC63LVD103 _Rev2.2
Pin Description
Pin Name TA+, TATB+, TBTC+, TCTD+, TDTE+,TETCLK+, TCLKTA0 ~ TA6 TB0 ~ TB6 TC0 ~ TC6 TD0 ~ TD6 TE0 ~ TE6 /PDWN Pin # 30, 31 28, 29 24, 25 20, 21 18, 19 22, 23 33,34,35,36,37,38,40 41,42,44,45,46,48,49 50,52,53,54,55,57,58 59,61,62,63,64,1,3 Type LVDS OUT LVDS OUT LVDS OUT LVDS OUT LVDS OUT LVDS OUT IN IN IN IN Pixel Data Inputs. LVDS Clock Out. LVDS Data Out. Description
4,5,6,8,9,11,16
13
IN
IN H: Normal operation, L: Power down (all outputs are Hi-Z) LVDS swing mode, VREF select.
LVDS Swing 350mV 350mV 200mV Small Swing Input Support N/A RS=VREFa N/A
RS VCC
RS
43
IN
0.6 ~ 1.4V GND
a. VREF is Input Reference Voltage.
R/F VCC CLKIN GND LVDS VCC LVDS GND PLL VCC PLL GND
60 51, 7 12 2, 10, 39, 47, 56 27 17, 26, 32 15 14
IN Power IN Ground Power Ground Power Ground
Input Clock Triggering Edge Select. H: Rising edge, L: Falling edge Power Supply Pins for TTL inputs and digital circuitry. Clock in. Ground Pins for TTL inputs and digital circuitry. Power Supply Pins for LVDS Outputs. Ground Pins for LVDS Outputs. Power Supply Pin for PLL circuitry. Ground Pins for PLL circuitry.
Copyright 2001-2006 THine Electronics, Inc. All rights reserved.
3
THine Electronics, Inc.
THC63LVD103 _Rev2.2
Absolute Maximum Ratings 1
Supply Voltage (VCC) CMOS/TTL Input Voltage CMOS/TTL Output Voltage LVDS Driver Output Voltage Junction Temperature Storage Temperature Range Resistance to soldering heat Maximum Power Dissipation @+25 C -0.3V ~ +4.0V -0.3V ~ (VCC + 0.3V) -0.3V ~ (VCC + 0.3V) -0.3V ~ (VCC + 0.3V) +125 C -55 C ~ +150 C +260 C /10sec 1.0W
1. "Absolute Maximum Ratings" are those valued beyond which the safety of the device can not be guaranteed. They are not meant to imply that the device should be operated at these limits. The tables of "Electrical Characteristics" specify conditions for device operation.
Copyright 2001-2006 THine Electronics, Inc. All rights reserved.
4
THine Electronics, Inc.
THC63LVD103 _Rev2.2
Electrical Characteristics CMOS/TTL DC Specifications
VCC = 3.0V ~ 3.6V, Ta = 0 C ~ +70 C Symbol VIH VIL VDDQ1 VREF VSH2 VSL2 IINC Parameter High Level Input Voltage Low Level Input Voltage Small Swing Voltage Input Reference Voltage Small Swing High Level Input Voltage Small Swing Low Level Input Voltage Input Current Small Swing (RS=VDDQ/2) VREF = VDDQ/2 VREF = VDDQ/2
0V V IN V CC
Conditions RS=VCC or GND RS=VCC or GND
Min. 2.0 GND 1.2
Typ.
Max. VCC 0.8 2.8
Units V V V
VDDQ/2 VDDQ/2 +100mV VDDQ/2 -100mV
10
V V A
Notes: 1VDDQ voltage defines max voltage of small swing input. It is not an actual input voltage. 2 Small swing signal is applied to TA[6:0], TB[6:0], TC[6:0], TD[6:0], TE[6:0] and CLKIN.
LVDS Transmitter DC Specifications
VCC = 3.0V ~ 3.6V, Ta = 0 C ~ +70 C Symbol Parameter Conditions Normal swing VOD Differential Output Voltage RL=100 RS=VCC Reduced swing RS=GND VOD VOC VOC IOS IOZ Change in VOD between complementary output states Common Mode Voltage Change in VOC between complementary output states Output Short Circuit Current Output TRI-STATE Current VOUT=0V, RL=100 /PDWN=0V, VOUT=0V to VCC RL=100 1.125 1.25 Min. 250 100 Typ. 350 200 Max. 450 300 35 1.375 35 -24
10
Units mV mV mV V mV mA A
Supply Current
VCC = 3.0V ~ 3.6V, Ta =0 C ~ +70 C Symbol Parameter Conditions RL=100,CL=5pF VCC=3.3V, RS=VCC ITCCG Transmitter Supply Current Gray Scale Pattern RL=100,CL=5pF VCC=3.3V, RS=GND Gray Scale Pattern f=85MHz f=135MHz f=85MHz f=135MHz Typ. 58 70 44 56 Max. 64 76 50 62 Units mA mA mA mA
Copyright 2001-2006 THine Electronics, Inc. All rights reserved.
5
THine Electronics, Inc.
THC63LVD103 _Rev2.2
Gray Scale Pattern CLKOUT Tx0 Tx1 Tx2 Tx3 Tx4 Tx5 Tx6
x=A,B,C,D,E
Worst Case Pattern CLKOUT Tx0 Tx1 Tx2 Tx3 Tx4 Tx5 Tx6
x=A,B,C,D,E
Copyright 2001-2006 THine Electronics, Inc. All rights reserved.
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THine Electronics, Inc.
THC63LVD103 _Rev2.2
Symbol
Parameter
Conditions RL=100,CL=5pF VCC=3.3V, RS=VCC f=85MHz f=135MHz f=85MHz f=135MHz
Typ. 69 87 55 73
Max. 75 93 61 79 10
Units mA mA mA mA A .
ITCCW
Transmitter Supply Current
Worst Case Pattern RL=100,CL=5pF VCC=3.3V, RS=GND Worst Case Pattern
ITCCS
Transmitter Power Down Supply Current
/PDWN = L
Copyright 2001-2006 THine Electronics, Inc. All rights reserved.
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THine Electronics, Inc.
THC63LVD103 _Rev2.2
Switching Characteristics
VCC = 3.0V ~ 3.6V, Ta = 0 C ~ +70 C Symbol tTCIT tTCP tTCH tTCL tTCD tTS tTH tLVT tTOP1 tTOP0 tTOP6 tTOP5 tTOP4 tTOP3 tTOP2 tTPLL Parameter CLK IN Transition time CLK IN Period CLK IN High Time CLK IN Low Time CLK IN to TCLK+/- Delay TTL Data Setup to CLK IN TTL Data Hold from CKL IN LVDS Transition Time Output Data Position0 Output Data Position1 Output Data Position2 Output Data Position3 Output Data Position4 Output Data Position5 Output Data Position6 Phase Lock Loop Set -0.2
t TCP ---------- - 0.2 7 t TCP 2 ---------- - 0.2 7 t TCP 3 ---------- - 0.2 7 t TCP 4 ---------- - 0.2 7 t TCP 5 ---------- - 0.2 7 t TCP 6 ---------- - 0.2 7
Min.
Typ.
Max. 5.0
Units ns ns ns ns ns ns ns
7.4 0.35tTCP 0.35tTCP 0.5tTCP 0.5tTCP 3tTCP 2.5 0 0.6 0.0
t TCP ---------7 t TCP 2 ---------7 t TCP 3 ---------7 t TCP 4 ---------7 t TCP 5 ---------7 t TCP 6 ---------7
125.0 0.65tTCP 0.65tTCP
1.5 +0.2
t TCP ---------- + 0.2 7 t TCP 2 ---------- + 0.2 7 t TCP 3 ---------- + 0.2 7 t TCP 4 ---------- + 0.2 7 t TCP 5 ---------- + 0.2 7 t TCP 6 ---------- + 0.2 7
ns ns ns ns ns ns ns ns ms
10.0
AC Timing Diagrams
TTL Input
CLK IN
90% 10% tTCIT
90% 10%
tTCIT
LVDS Output
Vdiff=(TA+)-(TA-) TA+ 5pF TALVDS Output Load tLVT tLVT 100 80% 80% 20%
Vdiff
20%
Copyright 2001-2006 THine Electronics, Inc. All rights reserved.
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THine Electronics, Inc.
THC63LVD103 _Rev2.2
AC Timing Diagrams TTL Inputs
tTCH tTCP
CLK IN
VCC/2
VCC/2
VCC/2
tTCL tTS tTH
Tx0-Tx6
VCC/2
VCC/2
tTCD
TCLK+
VOC
TCLK-
Note: CLK IN: for R/F=GND, denote as solid line, for R/F=VCC, denote as dashed line
Small Swing Inputs
tTCH
tTCP
VDDQ
CLK IN
VDDQ/2
VDDQ/2
VDDQ/2
tTCL tTS tTH
VREF GND
VDDQ
Tx0-Tx6
VDDQ/2
VDDQ/2
VREF GND
tTCD
TCLK+
VOC
TCLK-
Note: CLK IN: for R/F=GND, denote as solid line, for R/F=VCC, denote as dashed line
Copyright 2001-2006 THine Electronics, Inc. All rights reserved.
9
THine Electronics, Inc.
THC63LVD103 _Rev2.2
AC Timing Diagrams LVDS Output
Vdiff = 0V Vdiff = 0V
TCLK OUT (Differential) TA+/TA6 TA5 TA4 TA3 TA2 TA1 TA0
TB+/-
TB6
TB5
TB4
TB3
TB2
TB1
TB0
TC+/-
TC6
TC5
TC4
TC3
TC2
TC1
TC0
TD+/-
TD6
TD5
TD4
TD3
TD2
TD1
TD0
TE+/-
TE6
TE5
TE4
TE3
TE2
TE1
TE0
Previous Cycle
Next Cycle
tTOP1 tTOP0 tTOP6 tTOP5 tTOP4 tTOP3 tTOP2
Phase Lock Loop Set Time
/PDWN
2.0V 3.6V
VCC
3.0V tTPLL
CLKIN
Vdiff = 0V
TCLKx+/-
Copyright 2001-2006 THine Electronics, Inc. All rights reserved.
10
THine Electronics, Inc.
THC63LVD103 _Rev2.2
Package
64 Pin TQFP ,JEDEC
48
0.5TYP
49
33
0.22
THC63LVD103
64
INDEX
PIN No.1
16
17
1.00TYP
1.2MAX
UNITS: mm
Copyright 2001-2006 THine Electronics, Inc. All rights reserved.
11
"P"
10.0TYP
12.0TYP
THine Electronics, Inc.
THine
32
THC63LVD103 _Rev2.2
Notes to Users:
1. The contents of this data sheet are subject to change without prior notice. 2. Circuit diagrams shown in this data sheet are examples of application. Therefore, please pay sufficient attention when designing circuits. EVEN IF THERE ARE INCORRECT DESCRIPTIONS, THINE IS NOT RESPOSIBLE FOR ANY PROBLEM DUE TO THEM. Please note that incorrect descriptions sometimes cannot be corrected immediately if found. 3. THine's copyright, know-how and other intellectual property rights are included in this data sheet. Duplication of the data sheet and disclosure to other persons are strictly prohibited without THine's prior written permission. 4. THINE IS NOT RESPONSIBLE FOR ANY PROBLEMS OF INTELLECTUAL PROPERTY RIGHTS OCCURRING DURING THC63LVD103 USE, EXCEPT FOR DAMAGES RESULTING FROM INFRINGEMENT CAUSED ONLY BY THC63LVD103 WITHOUT ANY ITEM NOT SOLD BY THINE AND/OR ANY USERS' ACTION. THINE IS NOT RESPONSIBLE FOR PROBLEMS CAUSED BY SPECIFICATIONS SUPPLIED BY USERS. THC63LVD103 is designed on the premise that it should be used for ordinary electronic devices. Therefore, it shall not be used for applications that require extremely high-reliability (space equipment, nuclear control equipment, medical equipment that affects people's lives, etc.). In addition, when using THC63LVD103 for traffic signals, safety devices and control/safety units in transportation equipment, etc., appropriate measures should be taken. 5. THINE IS MAKING THE UTMOST EFFORT TO IMPROVE THE QUALITY AND RELIABILITY OF THINE'S PRODUCTS. HOWEVER, THERE IS A VERY SLIGHT POSSIBILITY OF FAILURE IN SEMICONDUCTOR DEVICES. To avoid damage to social or official organizations, much care should be taken to provide sufficient redundancy and fail-safe design. 6. No radiation-hardened design is incorporated in THC63LVD103. 7. Judgment on whether THC63LVD103 comes under strategic products prescribed by the Foreign Exchange and Foreign Trade Control Law is the user's responsibility. 8. This technical document was provisionally created during development of THC63LVD103, so there is a possibility of differences between it and the product's final specifications. When designing circuits using THC63LVD103, be sure to refer to the final technical documents.
THine Electronics, Inc. Wakamatsu Bldg, 6F 3-3-6, Nihombashi-Honcho, Chuo-ku, Tokyo, 103-0023 Japan Tel: 81-3-3270-0880 Fax: 81-3-3270-1771
Copyright 2001-2006 THine Electronics, Inc. All rights reserved.
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THine Electronics, Inc.

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